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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
DRAM
AVAILABLE AS MILITARY SPECIFICATIONS
* MIL-STD 883 * SMD Planned
1 MEG x 16 DRAM
3.3V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH
PIN ASSIGNMENT (Top View) 44/50-Pin SOJ/LCC/Gull Wing 450mil
FEATURES
* JEDEC- and industry-standard x16 timing, functions, pinouts and packages * High-performance CMOS silicon-gate process * Single +3.3V 0.3V power supply * All device pins are TTL-compatible * Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR), HIDDEN * BYTE WRITE access cycles * 1,024-cycle refresh (10 row-, 10 column-addresses) * Low power, 0.3mW standby; 180mW active, typical * Extended Data-Out (EDO) PAGE access cycle * 5V-tolerant I/Os (5.5V maximum VIH level)
Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC
OPTIONS
* Timing 60ns access (Contact Factory) 70ns access 80ns access * Refresh Rate Standard 16ms period * Packages Ceramic SOJ Ceramic Gull Wing Ceramic LCC
MARKING
-6 -7 -8 None ECJ No. 506 ECG No. 604 EC No. 213
NC NC WE RAS NC NC A0 A1 A2 A3 Vcc
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss
KEY TIMING PARAMETERS
SPEED -6 -7 -8
tRC 105ns 125ns 150ns tRAC 60ns 70ns 80ns tPC 25ns 30ns 40ns tAA 30ns 35ns 40ns tCAC 15ns 20ns 20ns tCAS 12ns 12ns 20ns
GENERAL DESCRIPTION
The AS4LC1M16 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x16 configuration. The AS4LC1M16 has both BYTE WRITE and WORD WRITE access cycles via two ?C?A/S pins (?C?A?S/L and ?C?A?S?H). These function in a similar manner to a single ?C?AS of other DRAMs in that either ?C?A?S/L or C?A?S?H will generate ?
AS4LC1M16 REV. 3/97 DS000020
an internal ?C?A/S. The AS4LC1M16 ?C?A/S function and timing are determined by the first ?C?A/S (?C?A?S/L or ?C?A?S?H) to transition LOW and the last ?C?A/S to transition back HIGH. Use of only one of the two results in a BYTE WRITE cycle. ?CASL transitioning ? ?/ LOW selects an access cycle for the lower byte (DQ1-DQ8) and ?C?A?S?H transitioning LOW selects an access cycle for the upper byte (DQ9-DQ16). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0 -A9) at a time. ?R?A/S is used to latch the first 10 bits and ?C?A/S the latter 10 bits. The ?C?A/S function also determines whether the cycle will be a refresh cycle (?R?A/S ONLY) or an active cycle (READ, WRITE or READ WRITE) once ?R?A/S goes LOW.
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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
GENERAL DESCRIPTION (continued)
The ?C?A/S/L and ?C?A/S?H inputs internally generate a ?C?A/S signal functioning in a similar manner to the single ?C?A/S input of other DRAMs. The key difference is each ?C?A/S input ( ?C?A/S/L and ?C?A/S?H ) controls its corresponding 8 DQ inputs during WRITE accesses. ?C?A/S/L controls DQ1 through DQ8 and ?C?A/S?H controls DQ9 through DQ16. The two ?C?A/S controls give the MT4LC1M16E5(S) both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or ?C?A/S (?C?AS/L or ?C?A/S/H), whichever occurs last. An EARLY WRITE / occurs when WE is taken LOW prior to either ?C?A/S falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE falls after ?C?A/S (?C?A/S/L or ?C?A/S/H) was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of ?O/E. During LATE WRITE or READ-MODIFY-WRITE cycles, ?O/E must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping ?O/E LOW, no write will occur, and the data-outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by ?O/E and ?W/E.
PAGE ACCESS
PAGE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-addressdefined page boundary. The PAGE cycle is always initiated with a row-address strobed-in by ?R?A/S followed by a column-address strobed-in by C?A/S. ?C?A/S may be toggled-in ? by holding ?R?A/S LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning ?R?A/S HIGH terminates the PAGE MODE of operation.
EDO PAGE MODE
The AS4LC1M16 provides EDO PAGE MODE which is an accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after ?C?A/S returns HIGH. EDO provides for ?C?A/S precharge time (tCP) to occur without the output data going invalid. This elimination of ?C?A/S output control provides for pipeline READs. FAST-PAGE-MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of ?C?A /S. EDO-PAGE-MODE DRAMs operate similar to FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after ?C?A/S goes HIGH during READs, provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while ?R?A/S and ?C?A/S are LOW, data will toggle from valid data to High-Z and back to the same valid data. If ?O/E is toggled or pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW, data will transition to and remain High-Z (refer to Figure 1).
RAS
V IH V IL
CASL/CASH
ADDR
DQ V IOH V IOL
,, ,,, ,,,,, ,,,,,C ,,,,, ,,,, , , ,, , , ,
V IH V IL V IH V IL ROW COLUMN (A) COLUMN (B) OLUMN (C) COLUMN (D) OPEN V IH V IL
OE
,,
VALID DATA (A) t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B) t OD t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to Low-Z if tOES is met.
The DQs remain High-Z until the next CAS cycle if tOEHC is met.
The DQs remain High-Z until the next CAS cycle if tOEP is met.
Figure 1 OUTPUT ENABLE AND DISABLE
AS4LC1M16 REV. 3/97 DS000020
, , ,,
,,
DON'T CARE UNDEFINED
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
EDO PAGE MODE (continued)
?W/E can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR'd, ?O/E must be used to disable idle banks of DRAMs. Alternatively, pulsing ?W/E to the idle banks during ?C?A/S HIGH time will also High-Z the outputs. Independent of ?O/E control, the outputs will disable after tOFF, which is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
RAS
CASL/CASH
ADDR
DQ V IOH V IOL
,, ,,, ,,,,,, ,,,,, ,,,,, ,,, , , ,, ,,
V IH V IL V IH V IL V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) OPEN V IH V IL V IH V IL
WE
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE
The DQs go to High-Z if WE falls, and if tWPZ is met, will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated).
Figure 2 ?W/E CONTROL OF DQs
,, ,, , ,,
DON'T CARE UNDEFINED
AS4LC1M16 REV. 3/97 DS000020
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by the use of ?C?A/S/L and ?C?A/S?H. Enabling ?C?A/S/L will select a lower BYTE access (DQ1-DQ8). Enabling ?C?A/S?H will select an upper BYTE access (DQ9-DQ16). Enabling both ?C?A/S/L and ?C?A/S?H selects a WORD WRITE cycle. The AS4LC1M16 may be viewed as two 1 Meg x 8 DRAMs that have common input controls, with the exception of the / ?C?A/S inputs. Figure 3 illustrates the BYTE WRITE and WORD WRITE cycles. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A ?C?A/S precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte is not allowed during the same cycle. However, an EARLY WRITE on one byte and, after a ?C?A/S precharge has been satisfied, a LATE WRITE on the other byte is permissable.
REFRESH
Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle (?R?A/S ONLY, CBR, or HIDDEN) so that all 1,024 combinations of RAS addresses are executed at least every ??/ 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing.
WORD WRITE RAS
LOWER BYTE WRITE
CASL
CASH
WE
LOWER BYTE (DQ1-DQ8) OF WORD
STORED DATA 1 1 0 1 1 1 1 1
INPUT DATA 0 0 1 0 0 0 0 0
INPUT DATA
STORED STORED DATA DATA 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
INPUT DATA 1 1 0 1 1 1 1 1
INPUT DATA
STORED DATA 1 1 0 1 1 1 1 1
UPPER BYTE (DQ9-DQ16) OF WORD
0 1 0 1 0 0 0 0
X X X X X X X X
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
X X X X X X X X ADDRESS 1
1 0 1 0 1 1 1 1
ADDRESS 0 X = NOT EFFECTIVE (DON'T CARE)
Figure 3 WORD AND BYTE WRITE EXAMPLE
AS4LC1M16 REV. 3/97 DS000020
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
WE CASL CASH DQ1 16 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER
10
CAS
DATA-IN BUFFER
DQ16
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10
COLUMNADDRESS BUFFER REFRESH CONTROLLER
COLUMN DECODER
16
1024
OE
16
SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 10 ROWADDRESS BUFFERS (10) ROW DECODER 1024 x 1024 x 16 MEMORY ARRAY
1024 x 16
10
1024
RAS
NO. 1 CLOCK GENERATOR
Vcc Vss
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
TRUTH TABLE
ADDRESSES FUNCTION Standby READ: WORD READ: LOWER BYTE READ: UPPER BYTE WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE: UPPER BYTE (EARLY) READ WRITE EDO-PAGE-MODE 1st Cycle READ 2nd Cycle Any Cycle EDO-PAGE-MODE 1st Cycle WRITE READ-WRITE HIDDEN REFRESH CBR REFRESH NOTE: 2nd Cycle 2nd Cycle READ WRITE EDO-PAGE-MODE 1st Cycle ?R?A/S H L L L L L L L L L L L L L L L>H>L L>H>L L H>L ?C?A/S/L H>X L L H L L H L H>L H>L L>H H>L H>L H>L H>L L L H L ?C?A/S/H H>X L H L L H L L H>L H>L L>H H>L H>L H>L H>L L L H L ?W/E X H H H L L L H>L H H H L L H>L H>L H L X H ?O/E X L L L X X X L>H L L L X X L>H L>H L X X X
tR tC
DQs High-Z Data-Out Lower Byte, Upper Byte, Data-Out Lower Byte, Data-Out Upper Byte Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z
NOTES
X ROW ROW ROW ROW ROW ROW ROW ROW n/a n/a ROW n/a ROW n/a ROW ROW ROW X
X COL COL COL COL COL COL COL COL COL n/a COL COL COL COL COL COL n/a X
1, 2 2 2 2 1 1 1, 2 1, 2 2 1, 3 4
?R?A/S-ONLY REFRESH
1. These WRITE cycles may also be BYTE WRITE cycles (either ?C?A/S/L or ?C?A/S/H active). 2. These READ cycles may also be BYTE READ cycles (either ?C?A/S/L or ?C?A/S/H active). 3. EARLY WRITE only. 4. Only one ?C?A/S must be active (?C?A/S/L or ?C?A/S/H).
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC pin Relative to VSS .............. -1.0V to +4.6V Voltage on NC, Inputs or I/O pins Relative to Vss ................................................. -1.0V to +5.5V Operating Temperature, TA (ambient) ..... TA(MIN)=-55C ...................................................................... TC(MAX)=125C Storage Temperature ................................... -55C to +150C Power Dissipation ............................................................. 1W Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 2, 3) (VCC = +3.3V 0.3V) PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs (including NC pins) Input Low (Logic 0) Voltage, all inputs (including NC pins) INPUT LEAKAGE CURRENT Any input 0V VIN 5.5V (All other pins not under test = 0V) OUTPUT LEVELS Output High Voltage (IOUT = -2.0mA) Output Low Voltage (IOUT = 2.0mA) VCC = 3.6V SYMBOL VCC VIH VIL II IOZ VOH VOL MIN 3.0 2.0 -1.0 -2 -10 2.4 0.4 MAX 3.6 VCC+1 0.8 2 10 UNITS V V V A A V V 4 NOTES
OUTPUT LEAKAGE CURRENT (Q is disabled; 0V VOUT 5.5V) VCC=3.6V
MAX PARAMETER/CONDITION STANDBY CURRENT: (TTL) (?R?A/S = ?C?A/S = VIH) STANDBY CURRENT: (CMOS) (?R?A/S = ?C?A/S = other inputs = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (?R?A/S, ?C?A/S address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (?R?A/S = VIL, ?C?A/S, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: ?R?A/S ONLY Average power supply current (?R?A/S cycling, ?C?A/S=VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (?R?A/S, ?C?A/S address cycling: tRC = tRC [MIN]) SYMBOL ICC1 ICC2 -6 2 1 -7 2 1 -8 2 1 UNITS NOTES mA mA
ICC3
170
155
140
mA
5, 6
ICC4
130
120
110
mA
5, 6
ICC5
160
145
130
mA
5, 6
ICC6
150
140
130
mA
5, 7
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
CAPACITANCE
PARAMETER Input Capacitance: Addresses Input Capacitance: ?R?A/S, ?C?A/S/L,?C?A/S/H, ?W/E, ?O/E Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 7 7 8 UNITS pF pF pF NOTES 8 8 8
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 2, 3, 6, 9, 10, 11, 12,) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER Access time from column-address Column-address set-up to ?C?A/S precharge Column-address hold time (referenced to ?R?A/S) Column-address setup time Row-address setup time Column-address to ?W/E delay time Access time from ?C?A/S Column-address hold time ?C?A/S pulse width ?C?A/S hold time (CBR REFRESH) Last ?C?A/S going LOW to first ?C?A/S to return HIGH ?C?A/S to output in Low-Z Data output hold after next ?C?A/S LOW ?C?A/S precharge time Access time from ?C?A/S precharge ?C?A/S to ?R?A/S precharge time ?C?A/S hold time ?C?A/S setup time (CBR REFRESH) ?C?A/S to ?W/E delay time Write command to ?C?A/S lead time Data-in hold time Data-in hold time (referenced to ?R?A/S) Data-in setup time Output disable Output Enable OE hold time from WE during READ-MODIFY-WRITE cycle ?/ ?/ ?O/E HIGH hold from ?C?A/S HIGH ?O/E HIGH pulse width -6 SYM tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDHR tDS tOD tOE tOEH tOEHC tOEP MIN 15 45 0 0 55 15 10 12 10 10 0 3 10 5 50 5 35 15 10 45 0 0 12 10 10 10,000 12 13 12 10 0 3 10 5 55 5 40 15 12 55 0 0 12 10 10 MAX 30 MIN 15 50 0 0 60 20 10,000 15 15 15 15 0 3 10 5 60 10 45 20 15 60 0 0 15 10 10 -7 MAX 35 MIN 25 60 0 0 65 20 10,000 -8 MAX 40
UNITS NOTES
35
40
40
15 15
15 20
15 20
ns ns ns ns 25 ns 25 ns 13 ns 14, 26 ns 25 ns 27 ns 7, 28 ns 29 ns 26 ns ns 15, 30 ns 26 ns 28 ns 28 ns 7, 25 ns 13, 25 ns 28 ns 16, 26 ns ns 16, 26 ns ns 17, 26 ns 18 ns 18 ns
AS4LC1M16 REV. 3/97 DS000020
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 2, 3, 6, 9, 10, 11, 12, 20) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER ?O/E LOW to ?C?A/S HIGH setup time Output buffer turn-off delay OE setup prior to RAS during HIDDEN REFRESH cycle ?/ ??/ EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from ?R?A/S ?R?A/S to column-address delay time Row-address hold time Column-address to ?R?A/S lead time ?R?A/S pulse width ?R?A/S pulse width (EDO PAGE MODE) Random READ or WRITE cycle time ?R?A/S to ?C?A/S delay time Read command hold time (referenced to ?C?A/S) Read command setup time Refresh period (1,024 cycles) ?R?A/S precharge time ?R?A/S to ?C?A/S precharge time Read command hold time (referenced to ?R?A/S) ?R?A/S hold time READ WRITE cycle time ?R?A/S to ?W/E delay time Write command to ?R?A/S lead time Transition time (rise or fall) Write command hold time Write command hold time (referenced to ?R?A/S) ?W/E command setup time Output disable delay from ?W/E Write command pulse width ?W/E pulse width to disable at ?C?A/S HIGH ?W/E hold time (CBR REFRESH) ?W/E setup time (CBR REFRESH) -6 SYM tOES tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAL tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP MIN 5 0 0 30 75 12 10 30 60 60 110 14 0 0 40 5 0 13 150 80 15 2 10 45 0 0 10 10 10 10 MAX 15 MIN 5 0 0 35 85 12 10 35 70 70 130 14 0 0 50 5 0 15 180 90 18 2 12 55 0 0 12 12 10 10 -7 MAX 15 MIN 10 0 0 40 90 15 10 40 80 80 150 16 0 0 60 5 0 20 200 105 20 2 15 60 0 0 15 15 10 10 -8 UNITS ns 20 ns ns ns ns 80 ns 40 ns ns ns 10,000 ns 100,000 ns ns 60 ns ns ns 16 ms ns ns ns ns ns ns ns 50 ns ns ns ns 20 ns ns ns ns ns MAX NOTES 20, 26 31 31 19 21
60 30
70 35
10,000 100,000 45
10,000 100,000 50
22, 25 23, 28 25
16
16
23 32 13
50
50
32 13, 25
13
15
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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
NOTES
1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is assured. 3. An initial pause of 100s is required after power-up followed by eight ?R?A/S refresh cycles (?R?A/S ONLY or CBR with ?W/E HIGH) before proper device operation is assured. The eight ?R?A/S cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. NC pins are assumed to be left floating and are not tested for leakage. 5. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. Column address changed once each cycle. 7. Enables on-chip refresh and address counters. 8. This parameter is sampled. VCC = +3.0V; f = 1 MHz. 9. AC characteristics assume tT = 2.5ns. 10. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 11. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2.0V. 13. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. ?O/E held HIGH and ?W/E taken LOW after ?C?A/S goes LOW results in a LATE WRITE (?O/E-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 14. Assumes that tRCD tRCD (MAX). 15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, ?C?A/S must be pulsed HIGH for tCP. 16. These parameters are referenced to ?C?A/S leading edge in EARLY WRITE cycles and ?W/E leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.
AS4LC1M16 REV. 3/97 DS000020
17. If ?O/E is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, ?W/E must be pulsed during ?C?A/S HIGH time in order to place I/O buffers in High-Z. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (?O/E HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if ?C?A/S remains LOW and ?O/E is taken back LOW after tOEH is met. If ?C?A/S goes HIGH prior to ?O/E going back LOW, the DQs will remain open. 19. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition, and is not referenced to VOH or VOL. It is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last. 21. Operation within the tRAD (MAX) limit ensures that tRAC (MIN) and tCAC (MIN) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA, provided tRCD is not exceeded. 22. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC, provided tRAD is not exceeded. 23. Either tRCH or tRRH must be satisfied for a READ cycle. 24. The first ?C?A/Sx edge to transition LOW. 25. Output parameter (DQx) is referenced to corresponding ?C?A/S input; DQ1-DQ8 by ?C?A/S/L and DQ9-DQ16 by ?C?A/S?H. 26. Each ?C?A/Sx must meet minimum pulse width. 27. The last ?C?A/Sx edge to transition HIGH. 28. Last falling ?C?A/Sx edge to first rising ?C?A/Sx edge. 29. Last rising ?C?A/Sx edge to first falling ?C?A/Sx edge. 30. Last rising ?C?A/Sx edge to next cycle's last rising ?C?A/Sx edge. 31. Last ?C?A/Sx to go LOW. 32. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, ?W/E = LOW and ?O/E = HIGH.
2-102
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP tRCD tCAS tCLCH tRRH tRP
RAS
CASL/CASH
ADDR
DQ
OE
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tOFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
,,, ,,, ,,,,, , ,, , , ,,,,,, ,, , , ,,,,, ,, ,,,, ,, ,, , ,, , ,, ,, , ,,
V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH tACH V IH V IL ROW COLUMN ROW tWRP tWRH tRCS tRCH WE V IH V IL NOTE 1 tAA tRAC tCAC tCLZ NOTE 2 tOFF V OH V OL OPEN VALID DATA OPEN t OE t OD V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCRP 5 tCSH 50 tOD 0 tOE tOFF 0 MAX 30 MIN 15 50 0 0 15 10,000 12 13 10 0 5 55 0 0 20 10,000 15 20 10 0 5 60 0 0 -7 MAX 35 MIN 20 60 0 0 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAC tRAD tRAH tRAL tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH tWRH tWRP MIN 12 10 30 60 110 14 0 0 40 0 13 10 10 -6 MAX 60 30 MIN 12 10 35 70 130 14 0 0 50 0 15 10 10 -7 MAX 70 35 MIN 15 10 40 80 150 20 0 0 60 0 15 10 10 -8 MAX 80 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10,000 45
10,000 50
10,000 60
15 15 15
15 20 15
20 20 20
AS4LC1M16 REV. 3/97 DS000020
2-103
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
EARLY WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS
CASL/CASH
ADDR
WE
V DQ V IOH IOL V IH V IL
OE
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
, , , ,,,,,, , , ,, ,,,,,,,, ,,,,,,,,, ,, , ,, , , ,,,,,, ,, , ,, , , ,, , , , , , , , , ,, , ,,
tCRP tRCD tCLCH V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH tACH V IH V IL ROW COLUMN ROW tCWL tRWL tWCR tWCH tWP tWCS tWRP tWRH V IH V IL NOTE 1 tDHR tDH tDS VALID DATA
,
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tACH 15 tAR 45 tASC 0 tASR 0 tCAH 10 tCAS 12 tCLCH 10 tCRP 5 tCSH 50 tCWL 15 tDH 10 tDHR 45 tDS 0 tRAD 12
AS4LC1M16 REV. 3/97 DS000020
MAX
10,000
30
-7 MIN MAX 15 50 0 0 12 13 10,000 10 5 55 15 12 55 0 12 35
-8 MIN MAX 20 60 0 0 15 20 10,000 10 5 60 20 15 55 0 15 40
-6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAH tRAL tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWRH tWRP MIN 10 30 60 110 14 40 13 15 10 45 0 10 10 10 MAX
10,000 45
-7 MIN MAX 10 35 70 10,000 130 14 50 50 15 15 12 55 0 12 10 10
-8 MIN MAX 10 40 80 10,000 150 20 60 60 0 20 15 60 0 15 10 10
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2-104
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tRP
RAS
CASL/CASH
ADDR
WE
, , ,,,, ,, ,, , , , , ,, ,, ,, , ,,,,, ,, , , ,, ,, ,, ,,, ,, ,, ,, , ,,,,, ,
tCRP tRCD tCAS, tCLCH V IH V IL tAR tRAD tRAL tASR tRAH tASC tCAH tACH V IH V IL ROW COLUMN ROW tRCS tRWD tCWD tCWL tRWL tWP tWRP tWRH tAWD V IH V IL NOTE 1 tAA tRAC tCAC t CLZ tDS tDH V DQ V IOH IOL OPEN VALID D OUT tOD VALID D IN OPEN tOE tOEH OE V IH V IL
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,
-7
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tAWD 55 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCRP 5 tCSH 50 tCWD 35 tCWL 15 tDH 10 tDS 0 tOD 0 MAX 30 MIN 15 50 0 0 60 15 10,000 12 13 10 0 5 55 40 15 12 0 0 20 10,000 15 20 10 0 5 60 45 20 15 0 0 -7 MAX 35 MIN 20 60 0 0 65 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOE tOEH tRAC tRAD tRAH tRAL tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP tWRH tWRP MIN 12 12 10 30 60 14 0 40 13 150 80 15 10 10 10 60 30 -6 MAX 15 MIN 12 12 10 35 70 14 0 50 15 180 90 15 12 10 10 70 35 -8 MAX 20 MIN 15 15 10 40 80 20 0 60 15 200 105 20 15 10 10 80 40 MAX 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10,000 45
10,000 50
10,000 60
15
15
20
AS4LC1M16 REV. 3/97 DS000020
2-105
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
EDO-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP CASL/CASH V IH V IL tRCD tCAS, t CLCH tPC tCP tCAS, t CLCH tCP tRSH tCAS, t CLCH tCP tRP
RAS
ADDR
WE
DQ
OE
, ,,, ,, ,, ,, , ,, , ,, , ,,,,,,,, ,
tAR tACH tRAD tRAH tASR tASC tCAH V IH V IL ROW COLUMN tWRP tWRH tRCS V IH V IL NOTE 1 tAA tRAC tCAC tCLZ V OH V OL OPEN tOE V IH V IL tOES
tACH
tASC
COLUMN
VALID DATA
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,,,,, , ,, , ,, , , ,, , , ,,, , ,,,
tACH tRAL tCAH tASC tCAH COLUMN ROW tRCH tAA tRRH tAA tCPA tCPA tCAC tCAC tCLZ tCOH tOEHC tOFF VALID DATA VALID DATA OPEN tOD tOE tOD tOES tOEP
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCOH 3 tCP 10 tCPA tCRP 5 tCSH 50 tOD 0 tOE tOEHC 10
AS4LC1M16 REV. 3/97 DS000020
-7 MAX 30 MIN 15 50 0 0 15 20 12 13 10 0 3 10 5 55 0 10 10,000 15 20 10 0 5 10 5 60 0 10 MAX 35 MIN 20 60 0 0
-8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOEP tOES tOFF tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRRH tRSH tWRH tWRP MIN 10 5 3 30 12 10 30 60 14 0 0 40 0 13 10 10
-6 MAX MIN 10 5 3 35 12 10 35 70 14 0 0 50 0 15 10 10
-7 MAX MIN 10 5 0 40 15 10 40 80 20 0 0 60 0 15 10 10
-8 UNITS ns ns 20 ns ns 80 ns 40 ns ns ns 100,000 ns 60 ns ns ns ns ns ns ns ns MAX
15 60 30
15 70 35
20 10,000
10,000
100,000 45
100,000 50
35
40
40
15 15
15 20
20 20
2-106
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP V IH V IL tCSH tPC tCP tCRP tRCD tCAS, tCLCH tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP tRP
RAS
CASL/CASH
ADDR
WE
V DQ V IOH IOL V IH V IL
OE
,, , , ,, ,, ,, ,, , , , ,,,, ,,, ,,, ,,,, ,, , , , , ,, ,,,,,,,,,,,,, ,,,,,, ,, , , , , , , ,
V IH V IL tAR tACH tRAD tASR tRAH tACH tASC tCAH tACH tASC tCAH tASC tRAL tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tCWL tWP tCWL tWP tCWL tWP tWCS tWCH tWCS tWCH tWCS tWCH tWRP tWRH V IH V IL NOTE 1 tWCR tDHR tDH tRWL tDS tDS tDH tDS tDH VALID DATA VALID DATA VALID DATA
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tACH 15 tAR 45 tASC 0 tASR 0 tCAH 10 tCAS 12 tCLCH 10 tCP 10 tCRP 5 tCSH 50 tCWL 15 tDH 10 tDHR 45 tDS 0 tPC 25 MAX MIN 15 50 0 0 12 13 10 10 5 55 15 12 55 0 30 -7 MAX MIN 20 60 0 0 15 20 10 10 5 60 20 15 55 0 40 -8 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAD tRAH tRAL tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWRH tWRP MIN 12 10 30 60 14 40 13 15 10 45 0 10 10 10 -6 MAX 30 -7 -8 MIN MAX MIN MAX UNITS 12 35 15 40 ns 10 10 ns 35 40 ns 70 125,000 80 100,000 ns 14 50 20 60 ns 50 60 ns 15 15 ns 15 20 ns 12 15 ns 55 60 ns 0 0 ns 12 15 ns 10 10 ns 10 10 ns
125,000 45
10,000
10,000
10,000
AS4LC1M16 REV. 3/97 DS000020
2-107
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH tCRP tRCD tCAS, tCLCH tCP t PC tPRWC NOTE 1 tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP tRP RAS
CASL/CASH
ADDR
WE
DQ
OE
,, ,, ,,,,,,, ,, , ,,,,, , ,, ,,,,, ,, ,,, , ,
V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN tRWD tRCS tCWL tWP tAWD tCWD tCWL tWP tAWD tCWD tWRP tWRH V IH V IL NOTE 2 tAA tAA tRAC tDH tDS tCPA tDH tDS tCAC tCLZ tCAC tCLZ V IOH V IOL OPEN VALID D OUT VALID D IN VALID D OUT VALID D IN tOD tOD tOE tOE V IH V IL
tASC
COLUMN
tAA
tCPA tCAC tCLZ
tOE
NOTE:
1. tPC is for LATE WRITE cycles only. 2. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,, ,, ,,,, , , ,, ,, , ,
tRAL tCAH ROW tRWL tAWD tCWL tWP tCWD tDH tDS VALID D OUT VALID D IN OPEN tOD t OEH
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tAA tAR 45 tASC 0 tASR 0 tAWD 55 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCP 10 tCPA tCRP 5 tCSH 50 tCWD 35 tCWL 15 tDH 10 tDS 0 tOD 0
AS4LC1M16 REV. 3/97 DS000020
-7 MAX 30 MIN 50 0 0 60 15 20 12 13 10 0 10 5 55 40 15 12 0 0 10,000 15 20 10 0 10 5 60 45 20 15 0 0 MAX 35 MIN 60 0 0 65
-8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOE tOEH tPC tPRWC tRAC tRAD tRAH tRAL tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP tWRH tWRP MIN 12 25 75 12 10 30 60 14 0 40 13 80 15 10 10 10
-6 MAX 15 MIN 12 30 85 60 30
-7 MAX 20 MIN
-8 UNITS ns 15 ns 40 ns 90 ns 80 ns 15 40 ns 10 ns 40 ns 80 100,000 ns 20 60 ns 0 ns 60 ns 15 ns 105 ns 20 ns 15 ns 10 ns 10 ns MAX 20
20 10,000
10,000
125,000 45
35
40
40
70 12 35 10 35 70 125,000 14 50 0 50 15 90 15 12 10 10
15
15
20
2-108
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP RAS V IH V IL t CSH t PC t CRP t RCD t CAS, tCLCH t CP t CAS, tCLCH t PC t CP t RSH t CAS, tCLCH t CP t RP
CASL/CASH
,, ,, ,, ,,, ,, ,, , , ,,,, , ,, ,, , ,, ,, ,
V IH V IL t AR t RAD tASR t RAH t ASC t CAH t ASC t CAH ADDR V IH V IL ROW COLUMN (A) COLUMN (B) tWRP tWRH t RCS t RCH WE V IH V IL NOTE 1 t AA t AA t RAC t CPA t CAC t CAC t COH t WHZ DQ V IOH V IOL OPEN VALID DOUT VALID DOUT t OE OE V IH V IL
t ACH t ASC t CAH
COLUMN (N) t WCS
t WCH
,,,
t RAL
ROW
t DS
t DH
VALID DIN
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,, ,, , ,
-7 MAX MIN 40 15 10 40 80 20 0 0 60 15 15 0 0 10 10
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCOH 3 tCP 10 tCPA tCRP 5 tCSH 50 tDH 10 tDS 0 tOE MAX 30 MIN 15 50 0 0 15 10,000 12 13 10 3 10 5 55 12 0 15 20 20 10,000 15 20 10 5 10 5 60 15 0 20 -7 MAX 35 MIN 20 60 0 0 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ tWRH tWRP MIN 25 12 10 30 60 14 0 0 40 13 10 0 0 10 10 -6 MAX 60 30 MIN 30 -8 UNITS ns 80 ns 40 ns ns ns 100,000 ns 60 ns ns ns ns ns ns ns 20 ns ns ns MAX
125,000 45
35
40
40
13
70 12 35 10 35 70 125,000 14 50 0 0 50 15 12 0 0 15 10 10
AS4LC1M16 REV. 3/97 DS000020
2-109
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
READ CYCLE (with ?W/E-controlled disable)
RAS V IH V IL tCSH
CASL/CASH
ADDR
DQ
OE
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,,, ,,, ,,,, ,, , , , ,, ,, ,,,,,,,, ,, ,, , ,, , ,, , , ,, , , , ,
tCRP tRCD tCAS, tCLCH tCP V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC V IH V IL ROW COLUMN COLUMN tWRP tWRH tRCS tRCH tWPZ tRCS WE V IH V IL NOTE 1 tAA tRAC tCAC tCLZ tWHZ tCLZ V OH V OL OPEN VALID DATA t OD OPEN t OE V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM MIN tAA tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCP 10 tCRP 5 tCSH 50 MAX 30 MIN 50 0 0 15 10,000 12 13 10 0 10 5 55 20 10,000 15 20 10 0 10 5 60 -7 MAX 35 MIN 60 0 0 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYM tOD tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ tWRH tWRP MIN 0 -6 MAX 15 15 60 30 45 MIN 0 -7 MAX 15 20 70 35 50 MIN 0 -8 MAX 15 20 80 40 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
12 10 14 0 0 0 10 10 10
13
12 10 14 0 0 0 12 10 10
15
15 10 20 0 0 0 15 10 10
20
AS4LC1M16 REV. 3/97 DS000020
2-110
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
?R?A/S-ONLY REFRESH CYCLE
tRC tRAS V IH V IL tRP
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
RAS
CASL/CASH
ADDR
WE
,, ,,,,,,,, ,,, , ,,,,,,,, ,,, ,, , , , ,
tCRP tRPC V IH V IL tASR tRAH V IH V IL ROW ROW V Q V OH OL OPEN tWRP tWRH tWRP tWRH V IH V IL NOTE 1
CBR REFRESH CYCLE (Addresses and ?O/E = DON'T CARE)
tRAS tRP
tRP RAS V IH V IL tRPC
tRAS
CASL and CASH
DQ
WE
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tWRP and tWRH are for system design reference only. The ?W/E signal is actually a "don't care" at ?R?A/S time during a CBR REFRESH. However, ?W/E should be held HIGH at ?R?A/S time during a CBR REFRESH to ensure compatibility with other DRAMs that require ?W/E HIGH at ?R?A/S time during a CBR REFRESH.
,,,,,,,,,,,,,,,,, ,, ,
tCP tCSR tCHR tRPC tCSR tCHR V IH V IL V OH V OL OPEN tWRP tWRH tWRP tWRH V IH V IL NOTE 2
TIMING PARAMETERS
-6 SYM tASR tCHR tCP tCRP tCSR tRAH MIN 0 10 10 5 5 10 MAX MIN 0 12 10 5 5 10 -7 MAX MIN 0 15 10 5 10 10 -8 MAX UNITS ns ns ns ns ns ns -6 SYM MIN MAX tRAS 60 10,000 tRC 105 tRP 40 tRPC 5 tWRH 10 tWRP 10 -7 MIN 70 125 50 5 10 10 MAX 10,000 MIN 80 150 60 5 10 10 -8 MAX 10,000 UNITS ns ns ns ns ns ns
AS4LC1M16 REV. 3/97 DS000020
2-111
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
HIDDEN REFRESH (?W/E = HIGH; ?O/E = LOW)
tRC tRAS RAS V IH V IL tRP
CYCLE 32
tRAS
CASL/CASH
TIMING PARAMETERS
-6 SYM tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD tOE MIN 45 0 0 15 10 10 0 5 0 12 12 0 5 0 MAX 30 MIN 50 0 0 -7
,, , ,,,,,, ,, ,,,, , , , , , ,, ,, ,, ,,, ,, , ,, ,, ,, , , , , , ,
tCRP tRCD tRSH tCHR V IH V IL tAR tRAD tASR tRAH tASC tRAL tCAH ADDR V IH V IL ROW COLUMN tAA tRAC tCAC tCLZ tOFF DQx V IOH V IOL OPEN VALID DATA OPEN tOE tOD OE V IH V IL tORD
DON'T CARE UNDEFINED
-8 MAX 35 MIN 60 0 0 20 15 15 0 5 0 20 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns SYM tOFF tORD tRAC tRAD tRAH tRAL tRAS tRC tRCD tRP tRSH MIN 3 0 12 10 30 60 105 14 40 13
-6 MAX 15 60 30 MIN 3 0 12 10 35 70 125 14 50 15
-7 MAX 15 70 35 MIN 3 0
-8 MAX 15 80 40 UNITS ns ns ns ns ns ns ns ns ns ns ns
10,000 45
15 15
15 20
20 20
15 10 40 10,000 80 145 50 20 60 15
10,000 60
AS4LC1M16 REV. 3/97 DS000020
2-112
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS (per Method 5005, Table I) 2, 8A, 10 1*, 2, 3, 7*, 8, 9, 10, 11 1, 2, 3, 4**, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11
MIL-STD-883 TEST REQUIREMENTS INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS (Method 5004) FINAL ELECTRICAL TEST PARAMETERS (Method 5004) GROUP A TEST REQUIREMENTS (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS (Method 5005)
* PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance.
AS4LC1M16 REV. 3/97 DS000020
2-113
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C 1 MEG x 16 DRAM
PRELIMINARY
AS4LC1M16 REV. 3/97 DS000020
2-114
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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